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ZGP323H Datasheet(PDF) 62 Page - Zilog, Inc.

Part No. ZGP323H
Description  Programmable input glitch filter for pulse reception
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Maker  ZILOG [Zilog, Inc.]
Homepage  http://www.zilog.com
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ZGP323H Datasheet(HTML) 62 Page - Zilog, Inc.

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ZGP323H
Product Specification
PS023803-0305
Functional Description
54
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the
Power-On Reset (POR) timer function. The POR time allows VDD and the oscilla-
tor circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
Power Fail to Power OK status, including Waking up from V
BO Standby
Stop-Mode Recovery (if D5 of SMR = 1)
WDT Timeout
The POR timer is 2.5 ms minimum. Bit 5 of the Stop-Mode Register determines
whether the POR timer is bypassed after Stop-Mode Recovery (typical for external
clock).
HALT Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5
remain active. The devices are recovered by interrupts, either externally or inter-
nally generated. An interrupt request must be executed (enabled) to exit HALT
Mode. After the interrupt service routine, the program continues from the instruc-
tion after HALT Mode.
STOP Mode
This instruction turns off the internal clock and external crystal oscillation, reduc-
ing the standby current to 10
µA or less. STOP Mode is terminated only by a
reset, such as WDT timeout, POR, SMR or external reset. This condition causes
the processor to restart the application program at address 000CH. To enter STOP
(or HALT) mode, first flush the instruction pipeline to avoid suspending execution
in mid-instruction. Execute a NOP (Opcode = FFH) immediately before the appro-
priate sleep instruction, as follows:


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