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ZGP323H Datasheet(PDF) 6 Page - Zilog, Inc.

Part No. ZGP323H
Description  Programmable input glitch filter for pulse reception
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Maker  ZILOG [Zilog, Inc.]
Homepage  http://www.zilog.com
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ZGP323H Datasheet(HTML) 6 Page - Zilog, Inc.

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ZGP323H
Product Specification
PS023803-0305
List of Figures
vi
Figure 34. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 35. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 36. Stop Mode Recovery Register 2 ((0F)DH:D2–D4, D6 Write Only) . . 61
Figure 37. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . . 62
Figure 38. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 39. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted) 66
Figure 40. T8 and T16 Common Control Functions ((0D)01H: Read/Write) . . . 67
Figure 41. T16 Control Register ((0D) 2H: Read/Write Except Where Noted) . 69
Figure 42. T8/T16 Control Register (0D)03H: Read/Write (Except Where
Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 43. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 44. Port Configuration Register (PCON)(0F)00H: Write Only) . . . . . . . . 72
Figure 45. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only,
D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 46. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4, D6 Write Only) 74
Figure 47. Watch-Dog Timer Register ((0F) 0FH: Write Only). . . . . . . . . . . . . . 75
Figure 48. Port 2 Mode Register (F6H: Write Only). . . . . . . . . . . . . . . . . . . . . . 75
Figure 49. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . 76
Figure 50. Port 0 and 1 Mode Register (F8H: Write Only) . . . . . . . . . . . . . . . . 77
Figure 51. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . 78
Figure 52. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . 79
Figure 53. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . 79
Figure 54. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 55. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 56. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 81
Figure 57. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 58. 20-Pin CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 59. 20-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 60. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 61. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 62. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 63. 28-Pin CDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 64. 28-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 65. 28-Pin SSOP Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 66. 40-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 67. 40-Pin CDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88


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