ZGP323H datasheet(45/107 Pages) ZILOG | Programmable input glitch filter for pulse reception

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ZGP323H

Product Specification

PS023803-0305

Functional Description

T8/T16_Logic/Edge _Detect

In TRANSMIT Mode, this field defines how the outputs of T8 and T16 are com-

bined (AND, OR, NOR, NAND).

In DEMODULATION Mode, this field defines which edge should be detected by

the edge detector.

Transmit_Submode/Glitch Filter

In Transmit Mode, this field defines whether T8 and T16 are in the PING-PONG

mode or in independent normal operation mode. Setting this field to “NORMAL

OPERATION Mode” terminates the “PING-PONG Mode” operation. When set to

10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1.

In DEMODULATION Mode, this field defines the width of the glitch that must be fil-

tered out.

Initial_T8_Out/Rising_Edge

In TRANSMIT Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1,

the output of T8 is set to 1 when it starts to count. When the counter is not enabled

and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This

ensures that when the clock is enabled, a transition occurs to the initial state set

by CTR1, D1.

In DEMODULATION Mode, this bit is set to 1 when a rising edge is detected in the

input signal. In order to reset the mode, a 1 should be written to this location.

Initial_T16 Out/Falling _Edge

In TRANSMIT Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If

it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only

in Normal or PING-PONG Mode (CTR1, D3; D2). When the counter is not enabled

and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures

that when the clock is enabled, a transition occurs to the initial state set by CTR1,

D0.

In DEMODULATION Mode, this bit is set to 1 when a falling edge is detected in

the input signal. In order to reset it, a 1 should be written to this location.

Modifying CTR1 (D1 or D0) while the counters are enabled

causes unpredictable output from T8/16_OUT.

CTR2 Counter/Timer 16 Control Register—CTR2(D)02H

Table 17 lists and briefly describes the fields for this register.

Note:

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