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ZGP323H Datasheet(PDF) 26 Page - Zilog, Inc. |
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ZGP323H Datasheet(HTML) 26 Page - Zilog, Inc. |
26 / 107 page ZGP323H Product Specification PS023803-0305 Pin Functions 18 Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. Port 0 (P07–P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. The Port 0 direction is reset to its default state following an SMR. Notes: |
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