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ZGP323H Datasheet(PDF) 70 Page - Zilog, Inc. |
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ZGP323H Datasheet(HTML) 70 Page - Zilog, Inc. |
70 / 107 page ![]() ZGP323H Product Specification PS023803-0305 Functional Description 62 Watch-Dog Timer Mode Register (WDTMR) The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8® CPU if it reaches its terminal count. The WDT must initially be enabled by execut- ing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum timeout period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4 through 7 are reserved (Figure 37). This register is accessible only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recovery (Figure 36). After this point, the register cannot be modified by any means (intentional or otherwise). The WDTMR cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0Fh. It is organized as shown in Figure 37. WDTMR(0F)0Fh Figure 37. Watch-Dog Timer Mode Register (Write Only) WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 23. D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 5 ms min. 01* 10 ms min. 10 20 ms min. 11 80 ms min. WDT During HALT 0OFF 1ON * WDT During Stop 0OFF 1ON * Reserved (Must be 0) * Default setting after reset |
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