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TPS61182RTET Datasheet(PDF) 3 Page - Texas Instruments |
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TPS61182RTET Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page DCTRL IFB3 SW V O 5 9 PGND 13 1 GND IFB4 2 3 4 6 7 8 10 11 12 14 15 16 QFNPACKAGE 16Pin3x3 (TOP VIEW) V BAT TPS61180/1/2 www.ti.com SLVS801E – DECEMBER 2007 – REVISED APRIL 2013 PINOUT TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NO. NAME 1 PGND I Power ground of the IC. Internally, it connects to the source of the PWM switch. 2 SW I This pin connects to the drain of the internal PWM switch, external Schottky diode and inductor. 3 VBAT I This pin is connected to the battery supply. It provides the pull-up voltage for the Fault pin and battery voltage signal. For TPS61181/2, this is also the input to the internal LDO. 4 VO O This pin monitors the output of the boost regulator. Connect this pin to the anode of the WLED strings. 5 ISET I The resistor on this pin programs the WLED output current. 6 Cin I Supply voltage of the IC. For TPS61181/2, it is the output of the internal LDO. Connect 0.1 μF bypass capacitor to this pin. For TPS61180, connect an external 3.3 V supply to power the IC. 7, 8, 9 IFB1-IFB3 I Current sink regulation inputs. They are connected to the cathode of WLEDs. The PWM loop regulates 12, 13, 14 IFB4-IFB6 the lowest VIFB to 400 mV. Each channel is limited to 25 mA current. 10 GND I Signal ground of the IC. 11 DCTRL I Dimming control logic input. The dimming frequency range is 100 Hz to 1 kHz. 15 EN I The enable pin to the IC. For TPS61181/2, a logic high signal turns on the internal LDO and enables the IC. Therefore, do not connect the EN pin to the Cin pin. 16 Fault I Gate driver output for an external PFET used for fault protection. It can also be used as signal output for system fault report. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS61180/1/2 |
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