4

2

3

8

12

11

10

9

VFB

VREG5

SS

GND

SW

SW

SW

16

15

14

13

1

5

6

7

VBST

TPS53511

PowerPAD

TM

TPS53511

SLUSBG4A – MARCH 2013 – REVISED JANUARY 2014

www.ti.com

DEVICE INFORMATION

PIN FUNCTIONS

PIN

I/O/P

DESCRIPTION

NAME

NO.

EN

6

I

Enable control input

GND

4

–

Signal ground pin

PG

5

O

Open drain power good output

7

Ground returns for low-side MOSFET. Also serves as inputs of current comparators. Connect PGND and

PGND

P

GND strongly together near the device.

8

SS

3

I/O

Soft-start control. An external capacitor should be connected to GND.

9

Switch node connection between high-side N-channel FET and low-side N-channel FET. Also serves as

SW

10

I/O

inputs to current comparator.

11

Supply input for high-side N-channel FET gate driver (boost terminal). Connect capacitor from this pin to

VBST

12

I

respective SW terminals. An internal PN diode is connected between VREG5 to VBST pin.

VCC

15

I

Supply input for 5V internal linear regulator for the control circuitry

VFB

1

I

Converter feedback input. Connect with feedback resistor divider.

13

VIN

I

Power input and connected to high side N-channel FET drain

14

VO

16

I

Connect to output of converter. This terminal is used for on-time adjustment.

VREG5

2

O

5.5-V power supply output. A capacitor (typical 1-µF) should be connected to GND.

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to

PowerPAD

–

PGND.

RGT PACKAGE

16 PIN

(TOP VIEW)

6

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