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HPA00295DDAR Datasheet(PDF) 4 Page - Texas Instruments |
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HPA00295DDAR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 36 page 1 2 3 4 8 7 6 5 PowerPAD BOOT NC NC VSENSE PH VIN GND ENA 4 TPS5430, TPS5431 SLVS632I – JANUARY 2006 – REVISED APRIL 2017 www.ti.com Product Folder Links: TPS5430 TPS5431 Submit Documentation Feedback Copyright © 2006–2017, Texas Instruments Incorporated 5 Pin Configuration and Functions DDA Package 8-Pin SOIC with Thermal Pad Top View Pin Functions PIN I/O DESCRIPTION NAME NO. BOOT 1 O Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin. NC 2, 3 — Not connected internally. VSENSE 4 I Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 I On/off control. Below 0.5 V, the device stops switching. Float the pin to enable. GND 6 — Ground. Connect to PowerPAD. VIN 7 — Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic capacitor. PH 8 I Source of the high side power MOSFET. Connected to external inductor and diode. PowerPAD — GND pin must be connected to the exposed pad for proper operation. |
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