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AT88SC25616C

5017DS–SMEM–7/04

Description

The AT88SC25616C member of the CryptoMemory family is a high-performance secure

memory providing 256 Kbits of user memory with advanced security and cryptographic

features built in. The user memory is divided into 16 2-byte zones, each of which may be

individually set with different security access rights or combined together to provide

space for 1 to 4 data files.

Smart Card Applications

The AT88SC25616C provides high security, low cost, and ease of implementation with-

out the need for a microprocessor operating system. The embedded cryptographic

engine provides for dynamic, symmetric-mutual authentication between the device and

host, as well as performing stream encryption for all data and passwords exchanged

between the device and host. Up to four unique key sets may be used for these opera-

tions. The AT88SC25616C offers the ability to communicate with virtually any smart

card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO

7816-3. Communication speeds up to 153,600 baud are supported by utilizing ISO

7816-3 Protocol and Parameter Selection.

Embedded Applications

Through dynamic, symmetric-mutual authentication, data encryption, and the use of

encrypted checksums, the AT88SC25616C provides a secure place for storage of sen-

sitive information within a system. With its tamper detection circuits, this information

remains safe even under attack. A 2-wire serial interface running at 1.5 MHz is used for

fast and efficient communications with up to 15 devices that may be individually

addressed. The AT88SC25616C is available in industry standard 8-lead packages with

the same familiar pinout as 2-wire serial EEPROMs.

Figure 1. Block Diagram

Pin Descriptions

Supply Voltage (V

The V

Clock (SCL/CLK)

In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device

with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an

“elementary time unit” (ETU) and is equal to 372/f.

When the synchronous protocol is used, the SCL/CLK input is used to positive edge

clock data into the device and negative edge clock data out of the device.

Random

Generator

Authentication,

Encryption and

Certification Unit

EEPROM

Answer to Reset

Data Transfer

Password

Verification

Reset Block

Asynchronous

ISO Interface

Synchronous

Interface

Power

Management

VCC

GND

SCL/CLK

SDA/IO

RST