2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

8

FEBRUARY 8, 2017

9DBL0242 / 9DBL0252 DATASHEET

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked

(CC) Architectures

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

-3dB point in High BW Mode (100MHz)

2

3.3

4

MHz

1,5

-3dB point in Low BW Mode (100MHz)

1

1.5

2

MHz

1,5

PLL Jitter Peaking

Peak Pass band Gain (100MHz)

0.8

2

dB

1

Duty Cycle

Measured differentially, PLL Mode

45

50

55

%

1

Duty Cycle Distortion

Measured differentially, Bypass Mode

-1

0.0

1

%

1,3

2500

3406

4500

ps

1

-100

8

100

ps

1,4

Skew, Output to Output

21

55

ps

1,4

PLL mode

15

50

ps

1,2

Additive Jitter in Bypass Mode

0.1

1

ps

1,2

Skew, Input to Output

Jitter, Cycle to cycle

PLL Bandwidth

BW

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Notes

PCIe Gen 1

23

32

86

ps (p-p) 1,2,3,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

0.6

0.8

3

ps

(rms)

1,2,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

1.7

2.1

3.1

ps

(rms)

1,2,5

PCIe Gen 3

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.4

0.48

1

ps

(rms)

1,2,5

PCIe Gen 4

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.4

0.48

0.5

ps

(rms)

1,2,5

PCIe Gen 1

0.0

0.01

ps

(p-p)

1,2,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

0.0

0.01

ps

(rms)

1,2,4,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

0.0

0.01

ps

(rms)

1,2,4,5

PCIe Gen 3

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.0

0.01

ps

(rms)

1,2,4,5

PCIe Gen 4

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.0

0.01

ps

(rms)

1,2,4,5

Phase Jitter,

PLL Mode

Additive

Phase Jitter,

Bypass mode

n/a