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TP3076 Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. TP3076
Description  COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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TP3076 Datasheet(HTML) 2 Page - National Semiconductor (TI)

 
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Connection Diagram
Pin Descriptions
Pin
Description
V
CC
+5V ±5% power supply.
V
BB
−5V ±5% power supply.
GND
Ground. All analog and digital signals are
referenced to this pin.
FS
X
Transmit Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
transmit time slot assigned to this device
(non-delayed data timing mode), or the start of
the transmit frame (delayed data timing mode
using the internal time-slot assignment
counter).
FS
R
Receive Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
receive time slot assigned to this device
(non-delayed data timing mode), or the start of
the receive frame (delayed data timing mode
using the internal time-slot assignment
counter).
BCLK
Bit clock input used to shift PCM data into and
out of the D
R and DX pins. BCLK may vary
from 64 kHz to 4.096 MHz in 8 kHz
increments, and must be synchronous with
MCLK.
MCLK
Master clock input used by the switched
capacitor filters and the encoder and decoder
sequencing logic. Must be 512 kHz,
1.536/1.544 MHz, 2.048 MHz or 4.096 MHz
and synchronous with BCLK.
VF
XI
The Transmit analog high-impedance input.
Voice frequency signals present on this input
are encoded as an A-law or µ-law PCM bit
stream and shifted out on the selected D
X pin.
VF
RO
The Receive analog power amplifier output,
capable of driving load impedances as low as
300
Ω (depending on the peak overload level
required). PCM data received on the assigned
D
R pin is decoded and appears at this output
as voice frequency signals.
Pin
Description
D
X1
This transmit data TRI-STATE® output
remains in the high impedance state except
during the assigned transmit time slot on the
assigned port, during which the transmit PCM
data byte is shifted out on the rising edges of
BCLK.
TS
X1
Normally this open drain output is floating in a
high impedance state except when a time-slot
is active on the D
X output, when the TSX1
output pulls low to enable a backplane
line-driver.
D
R1
This receive data input is inactive except
during the assigned receive time slot of the
assigned port when the receive PCM data is
shifted in on the falling edges of BCLK.
CCLK
Control Clock input. This clock shifts serial
control information into CI or out from CO
when the CS input is low, depending on the
current instruction. CCLK may be
asynchronous with the other system clocks.
CI
Control Data Input pin. Serial control
information is shifted into COMBO II on this
pin when CS is low. Byte 1 of control
information is always written into COMBO II,
while the direction of byte 2 data is
determined by bit 2 of byte 1, as defined in
Table 1.
CO
Control Data Output pin. Serial control or
status information is shifted out of COMBO II
on this pin when CS is low.
CS
Chip Select input. When this pin is low, control
information can be written to or read from
COMBO II via CI or CO.
IL3–IL0
Each Interface Latch I/O pin may be
individually programmed as an input or an
output determined by the state of the
corresponding bit in the Latch Direction
Register (LDR). For pins configured as inputs,
the logic state sensed on each input is latched
into the Interface Latch Register (ILR)
whenever control data is written to COMBO II,
while CS is low, and the information is shifted
out on the CO pin. When configured as
outputs, control data written into the ILR
appears at the corresponding IL pins.
Functional Description
POWER-ON INITIALIZATION
When power is first applied, power-on reset circuitry initial-
izes the COMBO II and puts it into the power-down state.
The gain control registers for the transmit and receive gain
sections are programmed for no output, the power amp is
disabled and the device is in the non-delayed timing mode.
The Latch Direction Register (LDR) is pre-set with all IL pins
programmed as inputs, placing the SLIC interface pins in a
high impedance state. The CO pin is in TRI-STATE condi-
tion. Other initial states in the Control Register are indicated
in Section 2.0.
DS009758-4
Order Number TP3076J
See NS Package Number J20A
www.national.com
2


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