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STM32F769NI Datasheet(PDF) 11 Page - STMicroelectronics |
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STM32F769NI Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 255 page  DocID029041 Rev 4 11/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of figures 13 List of figures Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx block diagram . . . . 19 Figure 3. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. VDDUSB connected to VDD power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 5. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 6. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30 Figure 7. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 34 Figure 11. STM32F76xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 12. STM32F76xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 13. STM32F76xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 14. STM32F769xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 15. STM32F769Ax/STM32F768Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 16. STM32F76xxx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 17. STM32F769xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 18. STM32F76xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 19. STM32F76xxx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 20. STM32F769xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 21. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 22. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 24. STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 25. STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 26. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 27. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 28. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 29. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 30. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 31. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 32. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 33. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 34. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 35. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 36. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 37. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 38. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 39. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 40. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 41. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 42. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 174 Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 174 Figure 45. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 |
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