SPC570S40E3 datasheet(11/68 Pages) STMICROELECTRONICS

Part #	SPC570S40E3

Description	Single issue 4-stage pipeline in-order execution core

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SPC570S40Ex, SPC570S50Ex

Block diagram

67

Table 3 summarizes the functions of all blocks present in the SPC570Sx series of

microcontrollers. Please note that the presence and number of blocks vary by device and

package.

Table 3. SPC570Sx series block summary

Block

Function

e200z0 CPU

Allows single clock instruction execution

Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the

eMIOS or from the PIT

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external

devices

Enhanced Direct Memory Access

(eDMA)

Performs complex data transfers with minimal intervention from a host

processor via 16 programmable channels.

DMACHMUX

Allows to route a defined number of DMA peripheral sources to the DMA

channels

Flash memory

Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area

network)

Supports the standard CAN communications protocol

PLL0

Output independent of core clock frequency

Frequency-modulated phase-

locked loop (PLL1)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

Provides priority-based preemptive scheduling of interrupt requests

AIPS

System bus to peripheral bus interface

RAM controller

Acts as an interface between the system bus and the integrated system RAM

System RAM

Supports read/write accesses mapped to the SRAM memory from any master

Flash memory controller

Acts as an interface between the system bus and the Flash memory module

Flash memory

Up to 512 KB of programmable, non-volatile Flash memory for code and 32 KB

for data

IRCOSC

Controls the internal 16 MHz RC oscillator system

XOSC

Controls the on-chip oscillator (XOSC) and provides the register interface for

the programmable features

JTAG Master

Provides software the option to write data for driving JTAG

JTAG Data Communication

Module

Provides the capability to move register data between the IPS and JTAG

domains

PASS

Programs a set of Flash memory access protections, based on user

programmable passwords

Sequence Processing Unit

Provides an on-device trigger functions similar to those found on a logic

analyzer

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

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