SPC56EL60X datasheet(8/165 Pages) STMICROELECTRONICS

Part #	SPC56EL60X

Description	Dual issue five-stage pipeline core

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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Introduction

SPC56ELx, SPC564Lx

8/165

DocID15457 Rev 12

1.3

Device comparison

Table 1. SPC56ELx/SPC564Lx device summary

Feature

SPC56EL60

SPC56EL54

CPU

Type

2 × e200z4

(in lock-step or decoupled operation)

Architecture

Harvard

Execution speed

0–120 MHz (+2% FM)

DMIPS intrinsic performance

>240 MIPS

SIMD (DSP + FPU)

Yes

MMU

16 entry

Instruction set PPC

Yes

Instruction set VLE

Yes

Instruction cache

4 KB, EDC

MPU-16 regions

Yes, replicated module

Semaphore unit (SEMA4)

Yes

Buses

Core bus

AHB, 32-bit address, 64-bit data

Internal periphery bus

32-bit address, 32-bit data

Crossbar Master × slave ports

Lock Step Mode: 4 × 3

Decoupled Parallel Mode: 6 × 3

Memory

Flash

1 MB, ECC, RWW

768 KB, ECC, RWW

Static RAM (SRAM)

128 KB, ECC

96 KB, ECC

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SPC56EL60X Datasheet(PDF) 8 Page - STMicroelectronics

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