TMS416409A, TMS417409A, TMS426409A, TMS427409A

4194304 BY 4-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES

SMKS893B – AUGUST 1996 – REVISED APRIL 1997

18

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

Address

W

OE

DQ1 – DQ4

tRC

Row

Column

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Valid Data Out

tRAS

tRP

tCSH

tT

tRCD

tRSH

tCRP

tCAS

tRAD

tASC

tRAL

tASR

tRCS

tCAH

tRRH

tRCH

tCAC

tCEZ

tAA

tCLZ

tRAC

tOEA

tROH

tOEZ

tCP

See Note A

Hi-Z

tRAH

tREZ

tWEZ

tWPE

tCAL

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

Figure 3. Read-Cycle Timing