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TMS416409A Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. TMS416409A
Description  4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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TMS416409A Datasheet(HTML) 6 Page - National Semiconductor (TI)

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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
RAS-only refresh
TMS416409A, TMS426409A
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
TMS417409A, TMS427409A
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS ( CBR ) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after
RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200
µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
test mode
The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low.
The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or
write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test
mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits
× 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced
by a factor of four for this series.


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