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TMS416409A Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. TMS416409A
Description  4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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TMS416409A Datasheet(HTML) 5 Page - National Semiconductor (TI)

 
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
extended data out
Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and for address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP, the
maximum RAS low time.
Extended data out does not place the data in / data out pins (DQ pins) into the high-impedance state with the
rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM
decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further
explain EDO operation benefit.
address: A0 – A11 ( TMS416409A and TMS426409A) and A0 – A10 (TMS417409A and TMS427409A)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip
by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For the TMS417409A
and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS.
Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling
edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the
column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 8).
write enable ( W )
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 9).
data in / data out (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE sections.


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