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XR16L2751IM Datasheet(PDF) 11 Page - Exar Corporation

Part # XR16L2751IM
Description  2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XR16L2751IM Datasheet(HTML) 11 Page - Exar Corporation

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XR16L2751
áç
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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
11
2.9
Crystal Oscillator or External Clock Input
The 2751 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum voltage at the pin should be VCC. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an
external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as shown in Figure 5) it can
extend its operation up to 50 MHz (6.25 Mbps serial data rate) at 5V with an 8X sampling rate.
For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at
http://www.exar.com.
2.10
Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by CLKSEL
hardware pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
C1
22-47pF
C2
22-47pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500K - 1M
XTAL1
XTAL2
2K
XT A L 1
XT A L 2
R1
VC C
E x te r nal C loc k
vcc
gnd


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