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VIPER53 Datasheet(PDF) 14 Page - STMicroelectronics |
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VIPER53 Datasheet(HTML) 14 Page - STMicroelectronics |
14 / 24 page VIPer53DIP / VIPer53SP 14/24 provides a soft start-up of the converter. The rising speed of the output voltage can be set through the value of C7. C4 and C6 values must be adjusted accordingly in order to ensure a correct start-up. CURRENT MODE TOPOLOGY The VIPer53 implements the conventional current mode control method for regulating the output voltage. This kind of feedback includes two nested regulation loops: The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS. When VS reaches VCOMP, the power switch is turned off. This structure is completely integrated as shown on the Block Diagram of page 1, with the current amplifier, the PWM comparator, the blanking time function and the PWM latch. The following formula gives the peak current in the Power MOSFET according to the compensation voltage: The outer loop defines the level at which the inner loop regulates peak current in the power switch. For this purpose, VCOMP is driven by the output of the error amplifier (Either the internal one in primary feedback configuration or a TL431 through an optocoupler in secondary feedback configuration, see figures 14 and 15) and is set accordingly the peak drain current for each switching cycle. As the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also provides a good converter start-up control. As the compensation voltage can be controlled to increase slowly during the start-up phase, the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise, without any overshoot. The simpler voltage mode structure which only controls the duty cycle, leads generally to high currents at start-up with the risk of transformer saturation. The compensation pin can also be used to limit the current capability of the device (See Current Limitation section). An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode. STANDBY MODE The device implements a special feature to address the low load condition. The corresponding function described hereafter consists of reducing the switching frequency by going into burst mode, with the following benefits: – It reduces the switching losses, thus providing low consumption on the mains lines. The device is compliant with “Blue Angel” and other similar standards, requiring less than 0.5 W of input power when in standby. – It allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on. For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM latch and the Power MOSFET in the off state as long as VCOMP remains below 0.5 V (See Block Diagram on page 1). If the output load requires a duty cycle below the one defined by the minimum turn on of the device, the error amplifier decreases its output voltage until it reaches this 0.5 V threshold (VCOMPoff). The Power MOSFET can be completely off for some cycles, and resumes normal operation as soon as VCOMP is higher than 0.5 V. The output voltage is regulated in burst mode. The corresponding ripple is not higher than the nominal one at full load. In addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to VCOMP value. Below 1 V (VCOMPbl), the blanking time increases to 400 ns, whereas it is 150 ns for higher voltages (See figure 11). The minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. This brutal change induces an hysteresis between normal operation and burst mode as shown on figure 16. When the output power decreases, the system reaches point 2 where VCOMP equals VCOMPbl. The minimum turn on time passes immediately from 350 ns to 600 ns, exceeding the effective turn on time that should be needed at such output power level. Therefore the regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst mode and to control the output voltage. The corresponding hysteresis can be seen on the switching frequency which passes from FSWnom which is the normal switching frequency set by the components connected to the OSC pin, to FSWstby. Note that this frequency is I Dpeak V COMP V COMP os – H COM P ---------------------------------------------- = |
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