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SCANPSC110F Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. SCANPSC110F
Description  SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

SCANPSC110F Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Table of Contents (Continued)
TABLE 2. Detailed Pin Description Table (Continued)
Pin #
I/O (Note 1)
& LCC)
Ground potential
14, 21
Power supply pins 0V.
Note 1: All pins are active HIGH unless otherwise noted.
Overview of SCANPSC110F Bridge Functions
Figure 1 shows the basic architecture of the ’PSC110F. The
device’s major functional blocks are illustrated here. The
TAP Controller, a 16-state state machine, is the central con-
trol for the device. The instruction register and various test
data registers can be scanned to exercise the various func-
tions of the ’PSC110F (these registers behave as defined in
IEEE Std. 1149.1).
The ’PSC110F selection controller provides the functionality
that allows the 1149.1 protocol to be used in a multi-drop en-
vironment. It primarily compares the address input to the slot
identification and enables the ’PSC110F for subsequent
scan operations.
The Local Scan Port Network (LSPN) contains multiplexing
logic used to select different port configurations. The LSPN
control block contains the Local Scan Port Controllers
(LSPC) for each Local Scan Port (LSP
1, LSP2, and LSP3).
This control block receives input from the ’PSC110F instruc-
tion register, mode register, and the TAP controller. Each lo-
cal port contains all four (4) boundary scan signals needed to
interface with the local TAPs.
The ’PSC110F is IEEE 1149.1-compatible, in that it supports
all required 1149.1 operations. In addition, it supports a
higher level of protocol, (Level 1), that extends the IEEE
1149.1 Std. to a multi-drop environment.
FIGURE 1. SCANPSC110F Bridge Architecture

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