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TNETV2501INPGF Datasheet(PDF) 70 Page - Texas Instruments |
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TNETV2501INPGF Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 197 page  Functional Overview 70 December 2002 − Revised November 2008 SPRS206K 3.9.5.4 PLL Divider1 Register (PLLDIV1) for SYSCLK1 This register controls the value of the divider D1 for SYSCLK1. It is in both the BYPASS and PLL paths. 15 14 8 D1EN Reserved R/W, 1 R, 0000000 75 4 0 Reserved PLLDIV1 R, 000 R/W, 00011 LEGEND: R = Read, W = Write, n = value at reset Figure 3−18. PLL Divider 1 Register Layout (0x1C8C) Table 3−15. PLL Divider 1 Register Bit Field Description BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION D1EN 15 R/W 1 Divider D1 enable D1EN = 0: Divider 1 disabled D1EN = 1: Divider 1 enabled Reserved 14:5 R 0000000000 Reserved. Reads return 0. Writes have no effect. PLLDIV1 4:0 R/W 00011 Divider D1 ratio (SYSCLK1 divider) PLLDIV1 = 00000: Divide by 1 PLLDIV1 = 00001: Divide by 2 PLLDIV1 = 00010: Reserved PLLDIV1 = 00011: Divide by 4 PLLDIV1 = 00100−11111: Reserved 3.9.5.5 PLL Divider2 Register (PLLDIV2) for SYSCLK2 This register controls the value of the divider D2 for SYSCLK2. It is in both the BYPASS and PLL paths. 15 14 8 D2EN Reserved R/W, 1 R, 0000000 75 4 0 Reserved PLLDIV2 R, 000 R/W, 00011 LEGEND: R = Read, W = Write, n = value at reset Figure 3−19. PLL Divider 2 Register Layout (0x1C8E) |
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