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SN65LVPE502A, SN65LVPE502B

SLLSEB3C – MARCH 2012 – REVISED NOVEMBER 2016

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Pin Functions – RGE Packages (continued)

PIN

DESCRIPTION

NAME

SN65LVPE502A

SN65LVPE502B

(2)

otherwise drive to Vcc/2 to assert mid-level state.

(3)

For SN65LVPE502B, pins 10 and 21 must be connected to GND, while 6 and 18 may be NC. For SN65LVPE502A, TI recommends at

least two of the four pins (6, 10, 18, 21) be connected to ground.

DE1, DE2

3, 16

16, 5

I

LVCMOS, selects de-emphasis settings for CH1 and CH2 per

EQ1, EQ2

2, 17

15, 7

I

LVCMOS, selects equalization settings for CH1 and CH2 per

OS1, OS2

4, 15

—

I

LVCMOS, selects output amplitude for CH1 and CH2 per

GND

6, 10, 18, 21,

Thermal Pad

10, 21, Thermal Pad

P

Supply ground

VCC

1,13

1, 13

P

Positive supply; must be 3.3 V ±10%

SN65LVPE502A RLL Package

24-Pin VQFN With Exposed Thermal Pad

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