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LMK04828 Datasheet(PDF) 6 Page - Texas Instruments |
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LMK04828 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 102 page  6 LMK04828-EP SNAS703 – APRIL 2017 www.ti.com Product Folder Links: LMK04828-EP Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 7.4 Thermal Information THERMAL METRIC(1) LMK04828-EP UNIT NKD (WQFN) 64 PINS RθJA Junction-to-ambient thermal resistance(2) 24.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance(3) 6.1 °C/W RθJB Junction-to-board thermal resistance(4) 3.5 °C/W ψJT Junction-to-top characterization parameter(5) 0.1 °C/W ψJB Junction-to-board characterization parameter(6) 3.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 0.7 °C/W (1) See the applications section of Power Supply Recommendations for ICC for specific part configuration and how to calculate ICC for a specific design. (2) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. (3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages. 7.5 Electrical Characteristics (3.15 V < VCC < 3.45 V, –55 °C < TA < +105°C. Typical values at VCC = 3.3 V, TA = 25 °C, at the recommended operating conditions and are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION ICC_PD Power-down supply current 1 3 mA ICC_CLKS Supply current(1) 14 HSDS 8 mA clocks enabled PLL1 and PLL2 locked. 565 670 mA CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS fCLKin Clock input frequency 0.001 750 MHz SLEWCLKin Clock input slew rate (2) 20% to 80% 0.15 0.5 V/ns VIDCLKin Differential clock input voltage(3) See Figure 4 AC-coupled 0.125 1.55 |V| VSSCLKin 0.25 3.1 Vpp VCLKin Clock input Single-ended input voltage AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 0 (Bipolar) 0.25 2.4 Vpp AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS) 0.35 2.4 Vpp |VCLKinX-offset| DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX) Each pin is AC-coupled, CLKin0/1/2 CLKinX_TYPE = 0 (Bipolar) 0 |mV| Each pin is AC-coupled, CLKin0/1 CLKinX_TYPE = 1 (MOS) 55 |mV| DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2) Each pin is AC-coupled CLKinX_TYPE = 1 (MOS) 20 |mV| VCLKin- VIH High input voltage DC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS) 2 VCC V VCLKin– VIL Low input voltage 0 0.4 V |
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