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PCM16C010 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. PCM16C010
Description  Configurable PC Card Interface Chip
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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PCM16C010 Datasheet(HTML) 5 Page - National Semiconductor (TI)

 
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30 Pinout Description (Continued)
TABLE 3-2 Serial EEPROM Interface Pins
Pin
Pin
Pin
Level
Internal
Description
Name
Type
No
Compatibility
Resistor
EEDIEEDO
IO
81
TTL 6 mA
Serial Data in tofrom EEPROM
EECS
O
83
CMOS 6 mA
EEPROM Chip Select
EESK
O
82
CMOS 6 mA
EEPROM Clock Freq e MCLK(0)32
Note
The Enable EEPROM function is performed in software by writing to the EEPROM Control Register The Enable EEPROM bit will default to low (disabled)
upon power on
TABLE 3-3 Card-Side Interface Pins
Pin
Pin
Pin
Level
Internal
Description
Name
Type
No
Compatibility
Resistor
LDATA(150)
IO
1 – 5 7 – 13
TTL 6 mA
Hold Circuit
Card-side Data Bus
97 – 100
(Note 1)
SPK
IN
I
86
TTL Schmitt
Input Audio Signal
RI
IN
I (Note 2)
23
TTL Schmitt
Ring Indicator for function 0
CIORD
O
19
CMOS 6 mA
IO read signals are passed through from HIORD
according to the expression shown below when a
valid address is decoded
CIORD
e
HIORD
a
REG
a
(CE1
CE2 )
CIOWR
O
18
CMOS 6 mA
IO write signals are passed through from HIOWR
according to the expression shown below when a
valid address is decoded
CIOWR
e
HIOWR
a
REG
a
(CE1
CE2 )
CWAIT
I (Note 2)
31
TTL
Card-side transaction wait state input
CS
O
30
CMOS 6 mA
Chip select for function
BHE
O
17
CMOS 6 mA
Byte high enable When de-asserted and CS( )
asserted an 8-bit access on LDATA(70) is in
progress This holds for both odd and even
addresses When asserted and CS( )
asserted a
16-bit access on LDATA(150) is in progress
READY
I
27
TTL
l
100k to VCC
Indicates that the function is either READY or
E
READY (ie - Busy) This signal is used to assert
the RdyBsy
bit in Pin Replacement Registers
CINT
I (Note 2)
29
TTL Schmitt
Card-side interrupt input signal
SRESET
O
28
CMOS 6 mA
Signals reset to Card-side function
IOCS16
I (Note 2)
26
TTL
This pin is asserted during an access to a function if
that function is capable of a 16-bit access
PCNTL
O
14
CMOS 6 mA
Power management control signals or general
output
MCLK
I
24
TTL Schmitt
Input clock for function
FCLK
O
25
CMOS 6 mA
Output clock signal for function This may be gated
onoff or be a divided value of MCLK
MEMWEH
O Tri
21
CMOS 6 mA
l
10k to VCC
Common Memory write output for upper byte of data
word
MEMWEL
O Tri
22
CMOS 6 mA
l
10k to VCC
Common Memory write output for lower byte of data
word
Note 1
The Hold Circuit will hold the signal to the logic value it was last set to when the line is TRI-STATE
This will insure that inputs do not float during a
TRI-STATE condition
Note 2
The CWAIT CINT RI
IN and IOCS16
pins are outputs (O) when the function is configured for the NAND Flash (NM29N16) Mode
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