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TMS320C6203BGNY300 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6203BGNY300 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 108 page  TMS320C6203B FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS086N − JANUARY 1999 − REVISED JULY 2006 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents parameter measurement information 46 . . . . . . . . . . . . . . . signal transition levels 46 . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 47 . . . . . . input and output clocks 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 52 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 55 . . . . . . . . . . . . . . . . . synchronous DRAM timing 59 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 69 . . . . . . . . . . . . . . . . . . . . . . . . . . expansion bus synchronous FIFO timing 70 . . . . . . . . . . . . expansion bus asynchronous peripheral timing 72 . . . . . . expansion bus synchronous host-port timing 75 . . . . . . . . expansion bus asynchronous host-port timing 81 . . . . . . . XHOLD/XHOLDA timing 83 . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 85 . . . . . . . . . . . . . DMAC, timer, power-down timing 97 . . . . . . . . . . . . . . . . . . JTAG test-port timing 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNZ, GLS, GNY and ZNY BGA packages (bottom view) 4 description 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C62x device compatibility 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . functional and CPU (DSP core) block diagram 9 . . . . . . . . . CPU (DSP core) description 10 . . . . . . . . . . . . . . . . . . . . . . . memory map summary 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 13 . . . . . . . . . . . . . . . . . . . . . DMA synchronization events 17 . . . . . . . . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 18 . . . . . . . . . . . . . . signal groups description 19 . . . . . . . . . . . . . . . . . . . . . . . . . . signal descriptions 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-down mode logic 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 44 . . . . . . . . . . . absolute maximum ratings over operating case temperature ranges 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 45 . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 45 . . |
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