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TLC5947DAPRG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TLC5947DAPRG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 33 page TLC5947 SBVS114B – JULY 2008 – REVISED JANUARY 2015 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME RHB NO. DAP NO. OUT17 18 22 O Constant-current output OUT18 19 23 O Constant-current output OUT19 20 24 O Constant-current output OUT20 21 25 O Constant-current output OUT21 22 26 O Constant-current output OUT22 23 27 O Constant-current output OUT23 24 28 O Constant-current output Serial data shift clock. Schmitt buffer input. Data present on the SIN pin are shifted into the shift register with the rising edge of the SCLK pin. Data are shifted to the MSB side by 1-bit SCLK 31 3 I synchronizing of the rising edge of SCLK. The MSB data appears on SOUT at the falling edge of SCLK. A rising edge on the SCLK input is allowed 100 ns after an XLAT rising edge. SIN 32 4 I Serial input for grayscale data Serial data output. This output is connected to the shift register placed after the MSB of the grayscale shift register. Therefore, the MSB data of the grayscale shift register appears at the SOUT 25 29 O falling edge of SCLK. This function reduces the data shifting errors caused by small timing margins between SIN and SCLK. VCC 28 32 — Power-supply voltage The data in the grayscale shift register are moved to the grayscale data latch with a low-to-high transition on this pin. When the XLAT rising edge is input, all constant-current outputs are forced XLAT 26 30 I off until the next grayscale display period. The grayscale counter is not reset to zero with a rising edge of XLAT. 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted. (1) (2) MIN MAX UNIT VCC Supply voltage: VCC –0.3 6.0 V IO Output current (dc) OUT0 to OUT23 38 mA VI Input voltage SIN, SCLK, XLAT, BLANK –0.3 VCC + 0.3 V SOUT –0.3 VCC + 0.3 V VO Output voltage OUT0 to OUT23 –0.3 33 V TJ(MAX) Operating junction temperature 150 °C Tstg Storage temperature –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all ±2500 pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification ±500 JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 4 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: TLC5947 |
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