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PCM16C00 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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PCM16C00 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 40 page  50 Functional Description (Continued) TABLE 5-1 Attribute Memory Map (Continued) Register Description Register Type Address (Hex) EEPROM Function 1 Base B Register PCMCIA Extension 0x104C No Unused PCMCIA Extension 0x104E – 0x1050 No Function 1 Limit Register PCMCIA Extension 0x1052 No Reserved for Future Use Registers PCMCIA Extension 0x1054 – 0x105E No 512 IO Memory Addressing National’s PCM16C00 uses a pair of address base and limit registers to fragment the IO Address space This allows I O transactions from the PCMCIA Host to be steered to the appropriate function TLF11669 – 4 IO Address Space FIGURE 5-1 IO Address Decoding for two functions on a PCMCIA Card 513 Common Memory Addressing National’s PCM16C00 does not specifically decode com- mon memory address accesses initiated by the host Rath- er it will pass host accesses HADDR(150) through to LADDR(150) and HDATA(150) through to LDATA(150) once the host is granted access to the card using the arbi- ter In addition the PCM16C00 will pass the HOE signal assertion through to the MEMOE signal and the host HWE signal assertion to the MEMWEH MEMWEL signals appropriately The assertion of MEMWEH MEM- WEL or both is determined by an 8-bit or 16-bit access and the address boundary as specified in the PCMCIA Specification The functions are free to use common memo- ry by arbitrating for the card local bus If granted the PCM16C00 will relinquish the LADDR(150) and LDA- TA(150) bus to the function If a function is mapped to common memory such as a FLASH device and requires further address lines it may use the HADDR(2516) lines from the PCMCIA socket as appropriate even though these signals do not go into the PCM16C00 These signals can be considered to be side- band to the PCM16C00 The card design is free to use ex- ternal decoding logic for common memory For an Ethernet LAN card that desires to have a FLASH device HADDR(16) may be used to fragment the Common Memory space into 2 pieces When HADDR(16) is zero (0) the LAN SRAM buffers (up to 64-kbyte max) may be select- ed When HADDR(16) is one (1) a 64-kbyte FLASH device may be selected This use of one address line does not require an additional IC If a FLASH device greater than 64k is desired minimal decoding logic would become neces- sary 52 REGISTERS 521 PCMCIA Registers The PCMCIA register’s context is for its respective function Each function (01) has its own set of Configuration Regis- ters so that each function may be configured and operated on independently from a programming model viewpoint CIS (CARD INFORMATION STRUCTURE) 0x000 – 0x03E2 When the PCM16C00 powers on the contents of the lower 2005-kbyte of the EEPROM are loaded into the device’s shadow RAM This not only allows attribute memory ac- cesses to the CIS but it also provides defaults for 10 PCM16C00 specific registers to be loaded This allows de- fault loading of parameters that are transparent to system or device software The best use is for the card manufacturer to determine what values these should be and program them into the EEPROM when the CIS is programmed Either system software such as Card ServicesSocket Services or device software may read and parse the CIS by accessing attribute memory on the PC Card If desired this software agent may write to the CIS or default EEPROM registers and if desired have these new values saved to the EEP- ROM The actual contents of the CIS and the static regis- ters is PC Card design dependent 9 |
Similar Part No. - PCM16C00 |
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Similar Description - PCM16C00 |
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