SN74SSTV32852

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003

4

POST OFFICE BOX 655303

recommended operating conditions (see Note 4)

MIN

NOM

MAX

UNIT

VCC

Supply voltage

VDDQ

2.7

V

VDDQ

Output supply voltage

2.3

2.7

V

VREF

Reference voltage (VREF = VDDQ/2)

1.15

1.25

1.35

V

VTT

Termination voltage

VREF–40mV

VREF

VREF+40mV

V

VI

Input voltage

0

VCC

V

VIH

AC high-level input voltage

Data inputs

VREF+310mV

V

VIL

AC low-level input voltage

Data inputs

VREF–310mV

V

VIH

DC high-level input voltage

Data inputs

VREF+150mV

V

VIL

DC low-level input voltage

Data inputs

VREF–150mV

V

VIH

High-level input voltage

RESET

1.7

V

VIL

Low-level input voltage

RESET

0.7

V

VICR

Common-mode input voltage range

CLK, CLK

0.97

1.53

V

VI(PP) Peak-to-peak input voltage

CLK, CLK

360

mV

IOH

High-level output current

–20

mA

IOL

Low-level output current

20

mA

TA

Operating free-air temperature

0

70

_C

NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential

inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,

literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

VIK

II = –18 mA

2.3 V

–1.2

V

VOH

IOH = –100 µA

2.3 V to 2.7 V

VDDQ–0.2

V

VOH

IOH = –16 mA

2.3 V

1.95

V

VOL

IOL = 100 µA

2.3 V to 2.7 V

0.2

V

VOL

IOL = 16 mA

2.3 V

0.35

V

II

All inputs

VI = VCC or GND

2.7 V

±5

µA

ICC

Static standby

RESET = GND

IO =0

27 V

10

µA

ICC

Static operating

RESET = VCC, VI = VIH(AC) or VIL(AC)

IO = 0

2.7 V

35

mA

Dynamic operating –

clock only

RESET = VCC, VI = VIH(AC) or VIL(AC),

CLK and CLK switching 50% duty cycle

46

µA/

MHz

ICCD

Dynamic operating –

per each data input

RESET = VCC, VI = VIH(AC) or VIL(AC),

CLK and CLK switching 50% duty cycle,

One data input switching at one-half clock

frequency, 50% duty cycle

IO = 0

2.7 V

12

µA/

clock

MHz/

D input

rOH

Output high

IOH = –20 mA

2.3 V to 2.7 V

7

20

Ω

rOL

Output low

IOL = 20 mA

2.3 V to 2.7 V

7

20

Ω

Data inputs

VI = VREF ± 310 mV

3

3.75

4.25

Ci

CLK, CLK

VICR = 1.25 V, VI(PP) = 360mV

2.5 V

3

3.5

4

pF

RESET

VI = VCC or GND

3.5

4.35

5

† All typical values are at VCC = 2.5 V, TA = 25°C.