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SN65LVDT2D Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LVDT2D Datasheet(HTML) 6 Page - Texas Instruments |
6 / 42 page SN65LVDS1, SN65LVDS2, SN65LVDT2 SLLS373L – JULY 1999 – REVISED DECEMBER 2014 www.ti.com 7.6 Receiver Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT Positive-going differential input voltage VITH+ 100 threshold See Figure 11 mV Negative-going differential input voltage VITH– –100 threshold IOH = –8 mA, VCC = 2.4 V 1.9 VOH High-level output voltage V IOH = –8 mA, VCC = 3 V 2.4 VOL Low-level output voltage IOL = 8 mA 0.25 0.4 V ICC Supply current No load, Steady state 4 7 mA VI = 0 V, other input = 1.2 V –20 –2 LVDS2 VI = 2.2 V, other input = 1.2 V, –3 –1.2 VCC = 3.0 V II Input current (A or B inputs) μA VI = 0 V, other input open –40 -4 LVDT2 VI = 2.2 V, other input open, –6 –2.4 VCC = 3.0 V Differential input current IID LVDS2 VIA = 2.4 V, VIB = 2.3 V –2 2 μA (IIA – IIB) LVDS2 VCC = 0 V, VIA = VIB = 2.4 V 20 Power-off input current (A or B II(OFF) μA inputs) LVDT2 VCC = 0 V, VIA = VIB = 2.4 V 40 RT Differential input resistance LVDT2 VIA = 2.4 V, VIB = 2.2 V 90 111 132 Ω CI Input capacitance VI = 0.4sin(4E6πt) + 0.5 V 5.8 pF CO Output capacitance VI = 0.4sin(4E6πt) + 0.5 V 3.4 pF (1) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. (2) All typical values are at 25°C and with a 2.7-V supply. 7.7 Driver Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.5 3.1 ns tPHL Propagation delay time, high-to-low-level output 1.8 3.1 ns RL = 100 Ω, CL = 10 pF, tr Differential output signal rise time 0.6 1 ns See Figure 13 tf Differential output signal fall time 0.7 1 ns tsk(p) Pulse skew (|tPHL – tPLH|) (2) 0.3 ns (1) All typical values are at 25°C and with a 3.3-V supply. (2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. 6 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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