1A

1Y

1

7

2A

2Y

3

5

3A

3Y

6

2

SN74LVC3G06

SCES364J – AUGUST 2001 – REVISED NOVEMBER 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Function Table

(Each Inverter)

INPUT

OUTPUT

A

Y

H

L

L

H

LOGIC DIAGRAM (POSITIVE LOGIC)

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Supply voltage range

–0.5

6.5

V

–0.5

6.5

V

–0.5

6.5

V

–0.5

6.5

V

Input clamp current

–50

mA

Output clamp current

–50

mA

Continuous output current

±50

mA

±100

mA

DCT package

220

DCU package

227

°C/W

YZP package

102

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3)

(4)

The package thermal impedance is calculated in accordance with JESD 51-7.

2

Submit Documentation Feedback

Copyright © 2001–2013, Texas Instruments Incorporated

Product Folder Links: SN74LVC3G06