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SN65HVD485EDGKR Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVD485EDGKR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 29 page SN65HVD485E SLLS612E – JUNE 2004 – REVISED DECEMBER 2015 www.ti.com 7.7 Power Dissipation Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 54 Ω, Input to D is a 10 Mbps 50% duty cycle square P(AVG) Average power dissipation 219 mW wave VCC at 5.5 V, TJ = 130°C Thermal shut-down junction TSD 165 °C temperature 7.8 Supply Current over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Driver and receiver enabled D at VCC or open or 0 V, DE at VCC, RE at 0 V, No load 2 mA ICC Driver and receiver D at VCC or open, DE at 0 V, RE at VCC 1 mA disabled (1) All typical values are at 25°C and with a 5-V supply. 7.9 Switching Characteristics: Driver over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 30 ns tPHL Propagation delay time, high-to-low-level output 30 ns tr Differential output signal rise time RL = 54 Ω, CL = 50 pF (see Figure 6) 25 ns tf Differential output signal fall time 25 ns tsk(p) Pulse skew (|tPHL – tPLH|) 5 ns Propagation delay time, high-impedance-to-high-level tPZH 150 ns output RL = 110 Ω, RE at 0 V (see Figure 7) Propagation delay time, high-level-to-high-impedance tPHZ 100 ns output Propagation delay time, high-impedance-to-low-level tPZL 150 ns output RL = 110 Ω, RE at 0 V (see Figure 8) Propagation delay time, low-level-to-high-impedance tPLZ 100 ns output Propagation delay time, shutdown-to-high-level tPZH(SHN) RL = 110 Ω, RE at VCC (see Figure 7) 2600 ns output tPZL(SHDN) Propagation delay time, shutdown-to-low-level output RL = 110 Ω, RE at VCC (see Figure 8) 2600 ns 7.10 Switching Characteristics: Receiver over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 200 ns tPHL Propagation delay time, high-to-low-level output 200 ns VID = -1.5 V to 1.5 V, CL = 15 pF tsk(p) Pulse skew (|tPHL – tPLH|) 6 ns (see Figure 11) tr Output signal rise time 3 ns tf Output signal fall time 3 ns tPZH Output enable time to high level 50 ns tPZL Output enable time to low level 50 ns CL = 15 pF, DE at 3 V, (see Figure 12 and Figure 13) tPHZ Output enable time from high level 50 ns tPLZ Output enable time from low level 50 ns Propagation delay time, shutdown-to-high-level tPZH(SHDN) 3500 ns output CL = 15 pF, DE at 0 V, (see Figure 14) Propagation delay time, shutdown-to-low-level tPZL(SHDN) 3500 ns output 6 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD485E |
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