P

S

S

P

SDA

SCK

t

BUF

t

LOW

t

r

t

f

t

HIGH

t

HDSTA

t

HDSTA

t

HDDAT

t

SUDAT

t

SUSTA

t

SUSTO

11

ONET8501PB

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SLLS910A – JULY 2008 – REVISED JUNE 2016

Product Folder Links: ONET8501PB

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Copyright © 2008–2016, Texas Instruments Incorporated

8.5 Programming

8.5.1 2-Wire Interface and Control Logic

The ONET8501PB uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are

driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include

100-k

Ω pullup resistors to VCC. For driving these inputs, TI recommends an open-drain output.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access

to read out control and status signals. The ONET8501PB is a slave device only which means that it can not

initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the

transmission. The master device provides the clock signal as well as the START and STOP commands. The

protocol for a data transmission is as follows:

1. START command

2. 7-bit slave address (1000100) followed by an eighth bit which is the data direction bit (R/W). A zero indicates

a WRITE and a 1 indicates a READ.

3. 8-bit register address

4. 8-bit register data word

5. STOP command

data transfer is shown in Figure 14. Parameters for Figure 13 are defined in Table 4.

Bus Idle: Both SDA and SCK lines remain HIGH

Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH,

defines a START condition (S). Each data transfer begins with a START condition.

Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH

defines a STOP condition (P). Each data transfer ends with a STOP condition; however, if the master still wishes

to communicate on the bus, it can generate a repeated START condition and address another slave without first

generating a STOP condition.

Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiver

acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The

transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the

acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the

acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t

acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a

STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time

later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by

the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the

master generates the STOP condition.