Electronic Components Datasheet Search |
|
ONET8501PB Datasheet(PDF) 3 Page - Texas Instruments |
|
ONET8501PB Datasheet(HTML) 3 Page - Texas Instruments |
3 / 32 page Not to scale Exposed Pad 1 GND 12 VCC 2 DIN+ 11 DOUT+ 3 DIN– 10 DOUT– 4 GND 9 VCC 3 ONET8501PB www.ti.com SLLS910A – JULY 2008 – REVISED JUNE 2016 Product Folder Links: ONET8501PB Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated 5 Description (continued) The ONET8501PB provides a gain of about 34 dB which ensures a fully differential output swing for input signals as low as 20 mVpp. The output amplitude can be adjusted to 350 mVpp, 650 mVpp, or 850 mVpp. To compensate for frequency-dependent loss of microstrips or striplines connected to the output of the device, programmable preemphasis is included in the output stage. A settable loss of signal detection and output disable are also provided. The device, available in RoHS compliant small footprint 3-mm × 3-mm, 16-pin VQFN package, typically dissipates less than 170 mW and is characterized for operation from –40°C to 100°C. 6 Pin Configuration and Functions RGT Package 16-Pin VQFN Top View Pin Functions PIN TYPE DESCRIPTION NAME NO. COC1 5 Analog Offset cancellation filter capacitor plus terminal. An external capacitor can be connected between this pin and COC2 to reduce the low frequency cutoff. To disable the offset cancellation loop, connect COC1 and COC2 together. COC2 6 Analog Offset cancellation filter capacitor minus terminal. An external capacitor can be connected between this pin and COC1 to reduce the low frequency cutoff. To disable the offset cancellation loop, connect COC1 and COC2 together. DIN+ 2 Analog-input Noninverted data input. Differentially 100 Ω terminated to DIN–. DIN– 3 Analog-input Inverted data input. Differentially 100 Ω terminated to DIN+. DIS 7 Digital-input Disables the output stage when set to a high level. DOUT– 10 CML-out Inverted data output. On-chip 50 Ω back-terminated to VCC. DOUT+ 11 CML-out Noninverted data output. On-chip 50 Ω back-terminated to VCC. GND 1,4, EP Supply Circuit ground. Exposed die pad (EP) must be grounded. LOS 8 Open-drain MOS High level indicates that the input signal amplitude is below the programmed threshold level. Open-drain output. Requires an external 10-k Ω pullup resistor to VCC for proper operation. RATE1 13 Digital-input Bandwidth selection for noise suppression. RATE0 14 Digital-input Bandwidth selection for noise suppression. SCK 15 Digital-input Serial interface clock input. Connect a pullup resistor (10 k Ω typical) to VCC. SDA 16 Digital-input Serial interface data input. Connect a pullup resistor (10 k Ω typical) to VCC. VCC 9, 12 Supply 3.3-V ± 10% supply voltage. |
Similar Part No. - ONET8501PB_17 |
|
Similar Description - ONET8501PB_17 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |