PRE_S

LO_0 ±

MUX_S0

SIA_0 ±

SIB_0 ±

LB0A

LB0B

SOA_0 ±

EQ

EQ

EQ

SOB_0 ±

LI_0 ±

PRE_S

PRE_L

PRE_S

LO_1 ±

MUX_S1

SIA_1 ±

SIB_1 ±

LB1A

LB1B

SOA_1 ±

EQ

EQ

EQ

SOB_1 ±

LI_1 ±

PRE_S

PRE_L

Pre-emphasis

Control

PreL_0

PreS_1

PreS_0

PreL_1

PRE_S

PRE_L

GND

Port 0

Port 1

RSV

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DS40MB200

SNLS144J – JUNE 2005 – REVISED JANUARY 2016

DS40MB200 Dual 4-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and

Receive Equalization

1 Features

3 Description

The DS40MB200 device is a dual signal conditioning

1

•

1-Gbps to 4-Gbps Low Jitter Operation

2:1 multiplexer (MUX) and 1:2 fan-out buffer designed

•

Fixed Input Equalization

for use in backplane-redundancy applications. Signal

•

Programmable Output Pre-Emphasis

conditioning features include continuous time linear

equalization (CTLE) and programmable output pre-

•

Independent Switch and Line Side Pre-Emphasis

emphasis, extending data communication in FR4

Controls

backplanes at rates up to 4 Gbps. Each input stage

•

Programmable Switch-Side Loopback Mode

has

a

fixed

equalizer

to

reduce

intersymbol

•

On-Chip Terminations

interference distortion from board traces.

•

3.3-V Supply

All output drivers have four selectable steps of pre-

•

ESD Rating of 6-kV HBM

emphasis to compensate for transmission losses from

long FR4 backplanes and reduce deterministic jitter.

•

48-leadless WQFN Package (7 mm × 7 mm)

The

pre-emphasis

levels

can

be

independently

•

0°C to +85°C Operating Temperature Range

controlled for the line-side and switch-side drivers.

The internal loopback paths from switch-side input to

2 Applications

switch-side output enable at-speed system testing. All

receiver inputs are internally terminated with 100-

Ω

•

Backplane or Cable Driver

differential

terminating

resistors.

All

drivers

are

•

Redundancy and Signal Conditioning Applications

internally terminated with 50

•

XAUI

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

DS40MB200

WQFN (48)

7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Block Diagram

All CML inputs and outputs must be AC coupled for optimal performance.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.