DS40MB200

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SNLS144J – JUNE 2005 – REVISED JANUARY 2016

Electrical Characteristics (continued)

over recommended operating supply and temperature ranges (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

AC CHARACTERISTICS

See Figure 6 for test circuit.

At 1.25 Gbps

2

Device random

RJ

Alternating-1-0 pattern.

At 4 Gbps

2

Pre-emphasis disabled.

Device deterministic

See Figure 6 for test circuit.

At 4 Gbps,

DJ

30

Pre-emphasis disabled.

PRBS7 pattern

Tested with alternating-1-0 pattern

4

Gbps

X

(5)

Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt

IN

generator driving the device.

(6)

Specified by design and characterization using statistical analysis.

(7)

Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation

peak deterministic jitter of the pattern generator driving the device.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Differential low-to-high transition

Measured with a clock-like pattern at 100 MHz,

80

ps

time

between 20% and 80% of the differential output

voltage. Pre-emphasis disabled.

Transition time is measured with fixture as

Differential high-to-low transition

80

ps

shown in Figure 6, adjusted to reflect the

time

transition time at the output pins.

Differential low-to-high propagation

0.5

2

ns

delay

Measured at 50% differential voltage from input

to output.

Differential high-to-low propagation

0.5

2

ns

delay

20

ps

Difference in propagation delay among data

200

ps

paths in the same device.

Difference in propagation delay between the

same output from devices operating under

500

ps

identical condition.

MUX switch time

loopback control to 50% of the valid differential

1.8

6

ns

output.

(1)

(2)

Specified by design and characterization using statistical analysis.

(3)

similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to

LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to

between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to

SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.

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