DS40MB200

SNLS144J – JUNE 2005 – REVISED JANUARY 2016

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6.5 Electrical Characteristics

over recommended operating supply and temperature ranges (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

LVCMOS DC SPECIFICATIONS

High level input voltage

2

V

Low level input voltage

−0.3

0.8

V

High level input current

−10

10

µA

Low level input current

75

94

124

µA

Pull-high resistance

35

k

Ω

RECEIVER SPECIFICATIONS

Below 1.25 Gbps

100

1750

AC-coupled differential signal.

Differential input

This parameter is not production

At 1.25 Gbps–3.125 Gbps

100

voltage range

tested.

Above 3.125 Gbps

100

1200

Common mode voltage

Measured at receiver inputs reference to ground.

1.3

V

at receiver inputs

Input differential

On-chip differential termination between IN+ or IN

−.

84

100

116

Ω

termination

DRIVER SPECIFICATIONS

PRES_1 = PRES_0 = 0

Output differential

PREL_1 = PREL_0 = 0

VODB

voltage swing without

1000

1200

Driver pre-emphasis disabled.

pre-emphasis

Running K28.7 pattern at 4 Gbps.

See Figure 6 for test circuit.

PREx_[1:0] = 00

0

Running K28.7 pattern at

PREx_[1:0] = 01

−3

Output pre-emphasis

PREx_[1:0] = 10

−6

x = S for switch side pre-

voltage ratio

emphasis control

dB

20 × log (VODPE /

x = L for line side pre-emphasis

VODB)

control

PREx_[1:0] = 11

−9

See Figure 8 on waveform.

See Figure 6 for test circuit.

Tested at

−9-dB pre-emphasis level, PREx[1:0] = 11

x = S for switch side pre-emphasis control

125

200

250

ps

x = L for line side pre-emphasis control

See Figure 3 on measurement condition.

On-chip termination from OUT+ or OUT

(4)

42

50

58

Ω

Output differential

On-chip differential termination between OUT+ and OUT

100

Ω

termination

Mismatch in output terminations at OUT+ and OUT

5%

E

termination resistors

Output common mode

2.7

V

voltage

POWER DISSIPATION

All outputs terminated by 100

Ω ±1%.

Power dissipation

1

W

PREL_[1:0] = 0, PRES_[1:0] = 0

(1)

(2)

K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and

–K28.5 code groups {110000 0101 001111 1010}

(3)

Specified by design and characterization using statistical analysis.

(4)

IN+ and IN

− are generic names refer to one of the many pairs of complementary inputs of the DS40MB200. OUT+ and OUT− are

as |IN+–IN

6

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