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DS40MB200 Datasheet(PDF) 4 Page - Texas Instruments

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Part # DS40MB200
Description  Dual 4-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and Receive Equalization
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DS40MB200 Datasheet(HTML) 4 Page - Texas Instruments

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DS40MB200
SNLS144J – JUNE 2005 – REVISED JANUARY 2016
www.ti.com
Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION(2)
NAME
NO.
SOB_0+
4
Inverting and noninverting differential outputs of mux_0 at the switch_B side. SOB_0+ and
O
SOB_0
3
SOB_0
− have an internal 50 Ω connected to VCC.
SOB_1+
28
Inverting and noninverting differential outputs of mux_1 at the switch_B side. SOB_1+ and
O
SOB_1
27
SOB_1
− have an internal 50 Ω connected to VCC.
CONTROL (3.3-V LVCMOS)
A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is
LB0A
47
I
internally pulled high.
A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is
LB0B
48
I
internally pulled high.
A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is
LB1A
23
I
internally pulled high.
A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is
LB1B
24
I
internally pulled high.
A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default
MUX_S0
37
I
state for mux_0 is switch A.
A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. Default
MUX_S1
13
I
state for mux_1 is switch A.
PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and
PREL_0
12
I
LO_1±). PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis
PREL_1
1
levels.
PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±,
PRES_0
36
I
SOB_0±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4
PRES_1
25
for switch side pre-emphasis levels.
Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND
RSV
26
I
through an external pull-down resistor.
POWER
Ground reference. Each ground pin must be connected to the ground plane through a low
5, 11, 17, 32,
GND
P
inductance path, typically with a via located as close as possible to the landing pad of the GND
41
pin.
Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the
GND
DAP
P
WQFN-48 package. It must be connected to the GND plane with at least 4 via to lower the
ground impedance and improve the thermal performance of the package.
VCC = 3.3 V ± 5%.
2, 8, 14, 20,
Each VCC pin must be connected to the VCC plane through a low inductance path, typically with
VCC
29, 35, 38,
P
a via located as close as possible to the landing pad of the VCC pin.
44
TI recommends to have a 0.01
μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC
pin to ground plane.
4
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