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PC87311A Datasheet(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87311A
Description  PC87311A/PC87312 (SuperI/OTM II/III) Floppy Disk Controller with Dual UARTs, Parallel Port, and IDE Interface
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87311A Datasheet(HTML) 10 Page - National Semiconductor (TI)

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10 Pin Description (Continued)
Symbol
Pin
IO
Function
MFM
53
IO
MFM
During a chip reset when in PS2 mode (IDENT low) this pin is sampled to select the PS2 mode
(MFM high) or the Model 30 mode (MFM low) An internal pull-up or external pull-down 10 kX resistor
will select between the two PS2 modes When the PC-AT mode is desired (IDENT high) MFM should
be left pulled high internally MFM reflects the current data encoding format when RESET is inactive
MFM e high FM e low Defaults to low after a chip reset This signal can also be configured as the
PUMP data separator diagnostic output via the Mode command (see Section 426)
MTR01
46 43
O
Motor Select 01
These are the motor enable lines for drives 0 and 1 and are controlled by bits
D7 – D4 of the Digital Output register They are active low outputs They are encoded with information to
control four FDDs when bit 4 of the Function Enable Register (FER) is set (See DR01 and Table 2-4
for more information)
PD0 – 7
94 – 91
IO
Parallel Port Data
These bidirectional pins transfer data to and from the peripheral data bus and the
parallel port Data Register These pins have high current drive capability (See DC Electrical
89–86
Characteristics)
PDIR
57
I
Parallel Port Direction
During reset the state of this pin determines the direction of the parallel port
data if the PTR7 e 0 The direction will be output (printer) when PDIR e 0 and PTR7 e 0 and it will be
input (scanner) when PDIR e 1 and PTR7 e 0 An internal pull-down resistor or 40 kX is on this pin
Usea10kX resistor to pull this pin to the required level during reset
PDWN
3I
Power Down
This multi-function pin will stop the clocks andor the external crystal based on the
selections made in the Power and Test Register bits 1-2 (See CSOUT for additional information)
PE
83
I
Paper End
This input is set high by the printer when it is out of paper This pin has a nominal 25 kX
pull-down resistor attached to it
POE
58
I
Parallel Port Output Enable
This pin is sensed during reset If it is low bit 7 of the Power and Test
Register (PTR7) is set high and the parallel port will operate in the Extended Mode In this mode
software determines the direction of parallel port data via the parallel port Control Register (CTR5) If
this pin is high (PTR7 e 0) then the Compatible Mode is selected and the data direction is determined
by the state of PDIR pin at reset An internal pull-down resistor of 40 kX is on this pin Use a 10 kX
resistor to pull this pin to the required level during reset
RD
19
I
Read
Active low input to signal a data read by the microprocessor
RDATA
35
I
Read Data
This input is the raw serial data read from the floppy disk drive
RI12
70 62
I
Ring Indicator
When low this indicates that a telephone ringing signal has been received by the
MODEM The RI signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI)
of the MODEM Status Register (MSR) for the appropriate serial channel Bit 6 is the complement of the
RI signal Bit 2 (TERI) of the MSR indicates whether the RI input has changed from low to high since the
previous reading of the MSR
Note
Whenever the TERI bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled
RTS12
74 66
O
Request to Send
When low this output indicates to the MODEM or data set that the UART is ready to
exchange data The RTS signal can be set to an active low by programming bit 1 (RTS) of the MODEM
Control Register to a high level A Master Reset operation sets this signal to its inactive (high) state In
the PC87312 loop mode operation holds this signal to its inactive state (See CFG0 – 4 for further
information) In the PC87311A loop mode operation holds this signal to its inactive state if the XTSEL
pin is high during reset If the XTSEL pin is low during reset the associated pin state is controlled by the
MCR1 bit during loop mode operation (See CFG0 – 4 for further information)
SIN12
75 67
I
Serial Input
This input receives composite serial data from the communications link (peripheral device
MODEM or data set)
SLCT
82
I
Select
This input is set high by the printer when it is selected This pin has a nominal 25 kX pull-down
resistor attached to it
SLIN
81
O
Select Input
When this signal is low it selects the printer This pin will be in a TRI-STATE condition
10 ns after a zero is loaded into the corresponding Control Register bit The system should pull this pin
high using a 47 kX resistor
10


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