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ONET8501V Datasheet(PDF) 3 Page - Texas Instruments |
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ONET8501V Datasheet(HTML) 3 Page - Texas Instruments |
3 / 29 page www.ti.com DIS RZTC TS SCK SDA BGV PD COMP MONP MONB 2 1 3 4 5 14 15 13 12 11 7 6 8 9 10 19 20 18 17 16 ONET 8501V 20PinQFN ONET8501V SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007 PACKAGE The ONET8501V is packaged in a small footprint 4mm × 4mm 20 pin RoHS compliant QFN package with a lead pitch of 0,5 mm. The pin out is shown below. 20 PIN QFN PACKAGE 4 mm × 4 mm (TOP VIEW) TERMINAL FUNCTIONS TERMINAL PIN NAME TYPE DESCRIPTION NO. 1 DIS Digital-in Disables bias, modulation and peaking currents when set to high state. Toggle to reset a fault condition. Recommend shorting pin to GND if disable feature is not used. 2 RZTC Analog Connect external zero TC 28.7k Ω resistor to ground (GND). Used to generate a defined zero TC reference current for internal DACs. 3 TS Analog-out Temperature sensor output. 4 SCK Digital -in 2-wire interface serial clock. Includes a pull-up resistor to VCC. 5 SDA Digital -in 2-wire interface serial data input. Includes a pull-up resistor to VCC. 6, 9, EP GND Supply Circuit ground. Exposed die pad (EP) must be grounded. 7 DIN+ Analog-in Non-inverted data input. On-chip differentially 100 Ω terminated to DIN–. Must be AC coupled. 8 DIN– Analog-in Inverted data input. On-chip differentially 100 Ω terminated to DIN+. Must be AC coupled. 10 FLT Digital-out Fault detection flag. LVCMOS output with source and sink capability. 11 BGV Anolog-out Buffered bandgap voltage with 1.16V output. This is a replica of the bandgap voltage at RZTC. For best matching, use the same 28.7k Ω resistor to GND as used at RZTC. 12 MONB Bias current monitor. Sources a 3.5% replica of the bias current. Connect an external resistor to ground (GND). If the voltage at this pin exceeds 1.16V a fault is triggered. Typically choose a resistor to give MONB voltage of 0.8V at the maximum desired bias current. Analog-out 13 MONP Photodiode current monitor. Sources a 27% replica of the photodiode current when PDR = 10, a 54% replica when PDR = 01, and a 270% replica when PDR=00. Connect an external resistor (5k Ω typical) to ground (GND). 14 COMP Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01 μF capacitor to ground. 15 PD Photodiode input. Pin can source or sink current dependent on register setting. Analog 16 BIAS Sinks average bias current for VCSEL in both APC and open loop modes. Connect to laser cathode through an inductor. BLM15HG102SN1D recommended. 17, 20 VCC Supply 3.3V ± 10% supply voltage Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): ONET8501V |
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