SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

INA219

SBOS448G – AUGUST 2008 – REVISED DECEMBER 2015

www.ti.com

Electrical Characteristics: (continued)

(1) = 1, unless otherwise noted.

INA219A

INA219B

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

Hysteresis

500

500

mV

OPEN-DRAIN DIGITAL OUTPUTS (SDA)

Logic 0 output level

0.15

0.4

0.15

0.4

V

High-level output leakage current

0.1

1

0.1

1

μA

POWER SUPPLY

Operating supply range

3

5.5

3

5.5

V

Quiescent current

0.7

1

0.7

1

mA

Quiescent current, power-down mode

6

15

6

15

μA

Power-on reset threshold

2

2

V

7.6 Bus Timing Diagram Definitions

(1)

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

SCL operating frequency

0.001

0.4

0.001

2.56

MHz

Bus free time between STOP and START

1300

160

ns

condition

Hold time after repeated START condition.

600

160

ns

After this period, the first clock is generated.

Repeated START condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

0

900

0

90

ns

Data setup time

100

10

ns

SCL clock LOW period

1300

250

ns

SCL clock HIGH period

600

60

ns

Data fall time

300

150

ns

Clock fall time

300

40

ns

Clock rise time

300

40

ns

Clock rise time for SCLK

≤ 100kHz

1000

ns

(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not ensured and not

production tested.

Figure 1. Bus Timing Diagram

6

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