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DDC232CZXGR Datasheet(PDF) 8 Page - Texas Instruments |
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DDC232CZXGR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 34 page  50pF 25pF 12.5pF VREF Range[2]Bit Range[1]Bit Range[0]Bit S RESET S REF2 S ADC1A S INTA S REF1 IN1 ESD Protection Diodes Input Current IntegratorB(sameasA) IntegratorA Photodiode 3pF ToConverter S INTB AdjustableFeedbackCapacitors(C ) F DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com DEVICE OPERATION operational amplifier. At the beginning of a conversion, the switches SA/D, SINTA, SINTB, SREF1, Basic Integration Cycle SREF2, and SRESET are set (see Figure 4). The topology of the front end of the DDC232 is an At the completion of an A/D conversion, the charge analog integrator as shown in Figure 3. In this on the integration capacitor (CF) is reset with SREF1 diagram, only input IN1 is shown. The input stage and SRESET (see Figure 4 and Figure 5a). This is consists of an operational amplifier, a selectable done during reset. In this manner, the selected feedback capacitor network (CF), and several capacitor is charged to the reference voltage, VREF. switches that implement the integration cycle. The Once the integration capacitor is charged, SREF1 and timing relationships of all of the switches shown in SRESET are switched so that VREF is no longer Figure 3 are illustrated in Figure 4. Figure 4 connected to the amplifier circuit while it waits to conceptualizes the operation of the integrator input begin integrating (see Figure 5b). With the rising stage of the DDC232 and should not be used as an edge of CONV, SINTA closes, which begins the exact timing tool for design. integration of side A. This process puts the integrator stage into its integrate mode (see Figure 5c). See Figure 5 for the block diagrams of the reset, integrate, wait, and convert states of the integrator Charge from the input signal is collected on the section of the DDC232. This internal switching integration capacitor, causing the voltage output of network is controlled externally with the convert pin the amplifier to decrease. The falling edge of CONV (CONV) and the system clock (CLK). For the best stops the integration by switching the input signal noise performance, CONV must be synchronized with from side A to side B (SINTA and SINTB). Prior to the the rising edge of CLK. It is recommended that CONV falling edge of CONV, the signal on side B was toggle within ±10ns of the rising edge of CLK. converted by the A/D converter and reset during the time that side A was integrating. With the falling edge The noninverting inputs of the integrators are of CONV, side B starts integrating the input signal. At connected to ground. Consequently, the DDC232 this point, the output voltage of the side A operational analog ground should be as clean as possible. In amplifier is presented to the input of the ∆Σ A/D Figure 3, the feedback capacitors (CF) are shown in converter (see Figure 5d). parallel between the inverting input and output of the Figure 3. Basic Integration Configuration for Input 1 8 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 |
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