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DLP3000 Datasheet(PDF) 9 Page - Texas Instruments |
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DLP3000 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 37 page  Micromirror Landed Duty Cycle 0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 30 40 50 60 70 80 D001 50/50 100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45 DLP3000 www.ti.com DLPS022B – JANUARY 2012 – REVISED MARCH 2015 Figure 1. Max Recommended Array Temperature – Derating Curve 6.5 Thermal Information THERMAL METRIC(1) MIN NOM MAX UNIT Thermal resistance from active micromirror array to TC3 5 °C/W (1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. 6.6 Electrical Characteristics over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage(1) VCC = 2.375 V, IOH = –20 mA 1.7 V VOL Low-level output voltage(1) VCC = 2.625 V, IOL = 15 mA 0.4 V IOH High-level output current VOH = 1.7 V –15 mA IOL Low-level output current VOL = 0.4 V 14 mA IIL Low-level input current VREF = 1.95 V, VI = 0 V –1.6 nA IIH High-level input current VREF = 1.95 V, VI = VREF 1.9 nA IREF Current into VREF pin VREF = 1.95 V, ƒDCLK = 77 MHz 0.7 mA ICC Current into VCC pin VCC = 2.625 V, ƒDCLK = 77 MHz 55 mA IOFFSET Current into VOFFSET pin (2) VOFFSET = 8.75 V 1 mA IBIAS Current into VBIAS pin (2) VBIAS = 17 V 1.6 mA IRESET Current into VRESET pin (2) VRESET = –11 V 1.5 mA PREF Power into VREF pin (3) VREF = 1.95 V, ƒDCLK = 77 MHz 1.5 mW PCC Power into VCC pin (3) VCC = 2.625 V, ƒDCLK = 77 MHz 144 mW POFFSET Power into VOFFSET pin (3) VOFFSET = 8.75 V 9 mW PBIAS Power into VBIAS pin (3) VBIAS = 17 V 27.2 mW PRESET Power into VRESET pin (3) VRESET = –11 V 18 mW CI Input capacitance ƒ = 1 MHz 10 pF CO Output capacitance ƒ = 1 MHz 10 pF (1) Applies to LVCMOS pins only. (2) Exceeding the maximum allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw. See the Micromirror Array Temperature Calculation for further details. (3) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the Micromirror Array Temperature Calculation for further details. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DLP3000 |
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