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INA230 Datasheet(PDF) 5 Page - Texas Instruments |
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INA230 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 37 page A1 A0 ALERT SDA IN- BUS GND V S+ 1 2 3 4 12 11 10 9 INA230 www.ti.com SBOS601 – FEBRUARY 2012 PIN CONFIGURATIONS RGT PACKAGE QFN-16 (TOP VIEW) PIN DESCRIPTIONS PIN ANALOG/DIGITAL INPUT/OUTPUT NAME NO. DESCRIPTION Address pin. Connect to GND, SCL, SDA, or VS. Table 7 shows pin settings and A0 2 Digital input corresponding addresses. Address pin. Connect to GND, SCL, SDA, or VS. Table 7 shows pin settings and A1 1 Digital input corresponding addresses. ALERT 3 Digital output Multi-functional alert, open-drain output. GND 10 Analog Ground NC 6, 7, 8, 14, 15, 16 — No internal connection SCL 5 Digital input Serial bus clock line, open-drain input. SDA 4 Digital input/output Serial bus data line, open-drain input/output. BUS 11 Analog input Bus voltage input IN – 12 Analog input Negative differential shunt voltage input. Connect to load side of shunt resistor. IN+ 13 Analog input Positive differential shunt voltage input. Connect to supply side of shunt resistor. VS 9 Analog Power supply, 2.7 V to 5.5 V. Thermal Pad This pad can be connected to ground or left floating. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): INA230 |
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