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PC87200160A Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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PC87200160A Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 33 page  10 www.national.com 5.0 Pin Descriptions (Continued) 5.3.3 PCI Interface Signals Signal Name Pin No. Type Description AD[31:0] 65,66, 67,68, 69,70, 73,74, 77,78, 81,82, 83,84, 85,86, 100,101, 102,103, 104,107, 108,109, 111,112, 115,116, 117,118, 119,120 I/O t/s PCI Address/Data AD[31:0] is a physical address during the first clock of a PCI transaction; it is the data during subsequent clocks. When the PC87200 is a PCI master, AD[31:0] are outputs during the address and write data phases, and are inputs during the read data phase of a transac- tion. When the PC87200 is a PCI slave, AD[31:0] are inputs during the address and write data phases, and are outputs during the read data phase of a transaction. C/BE[3:0]# 75,87, 99,110 I/O t/s PCI Bus Command and Byte Enables During the address phase of a PCI transaction, C/BE[3:0]# defines the bus com- mand. During the data phase of a transaction, C/BE[3:0]# are the data byte en- ables. C/BE[3:0]# are outputs when the PC87200 is a PCI master and are inputs when it is a PCI slave. IDSEL 76 I Initialization Device Select It is used as a chip select during configuration read and write transactions. FRAME# 88 I/O t/s PCI Cycle Frame FRAME# is asserted to indicate the start and duration of a transaction. It is deas- serted on the final data phase. FRAME# is an input when the PC87200 is a PCI slave. IRDY# 91 I/O t/s PCI Initiator Ready IRDY# is driven by the master to indicate valid data on a write transaction, or that it is ready to receive data on a read transaction. When the PC87200 is a PCI slave, IRDY# is an input that can delay the begin- ning of a write transaction or the completion of a read transaction. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. TRDY# 92 I/O t/s PCI Target Ready TRDY# is asserted by a PCI slave to indicate it is ready to complete the current data transfer. TRDY# is an input that indicates a PCI slave has driven valid data on a read or a PCI slave is ready to accept data from the PC87200 on a write. TRDY# is an output that indicates the PC87200 has placed valid data on AD[31:0] during a read or is ready to accept the data from a PCI master on a write. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. STOP# 94 I/O t/s PCI Stop As an input, STOP# indicates that a PCI slave wants to terminate the current transfer. The transfer will be aborted, retried, or disconnected. As an output, STOP# is asserted with TRDY# to indicate a target disconnect, or without TRDY# to indicate a target retry. |
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