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PC87200 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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PC87200 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 33 page  3.0 Device Overview (Continued) 6 www.national.com When a legacy ISA bus DMA request is asserted, the PC87200 will transmit that request to the PC/PCI Primary Bus Arbiter by encoding it and driving it out the PC87200’s PCPCIREQ# according to the above; first PCPCIREQ# will be driven low for one PCICLK period to indicate that the serial encoded request transfer is starting. Then the PC87200 will drive each of the next eight bits with the value of its corresponding DREQ. (NOTE: Channel 4 will always be driven low.) At the end of the request sequence, the PC87200 will continue to drive its PCPCIREQ# signal active, indicating that the request is still being maintained. In response to the request sequence, the PC/PCI Primary Bus Arbiter will respond with a PC/PCI DMA encoded grant transfer when it is granting the PCI bus for a PC/PCI DMA transfer cycle. The PC/PCI encoded grant transfer will begin when the PC/PCI Primary Bus Arbiter drives PCPCIGNT# low for one PCICLK period to indicate the start of the grant sequence; then the next three PCPCIGNT# signal PCICLK periods will then contain the encoded grant value, indicating which legacy ISA DMA channel is being granted the PC Bus. After receiving a valid grant from the PC/PCI DMA Arbiter, the PC87200 will recognize the following I/O accesses as DMA I/O Reads(Writes) from (to) the granted legacy ISA DMA channel. PCI bus address bit 2 (A2) indicates if the cycle is to be a Terminal Count cycle or not. For Normal DMA Cycles, PCI bus I/O Reads and Writes will be translated to legacy ISA DMA Reads and Writes respectively. For Verify DMA Cycles, only PCI bus I/O Reads will be translated to legacy ISA DMA Verify cycles. 3.5.4 Clock Generation The PC87200 generates the ISA clock using PCI clock sig- nal (typically 33 MHz). A PCICLK divisor (3,4) is programmable through PCI con- figuration register to generate the ISA clock signal. This provides support for the generation of ISACLK frequencies 8.33 MHz and 11 MHz off of a 33MHz PCICLK. Figure 3. shows a block diagram for clock generation within the PC87200. bit 2 bit 1 bit 0 Channel Granted 0 0 0 DMA Channel 0 (DACK0#) 0 0 1 DMA Channel 0 (DACK1#) 0 1 0 DMA Channel 0 (DACK2#) 0 1 1 DMA Channel 0 (DACK3#) 1 0 0 RESERVED 1 0 1 DMA Channel 0 (DACK5#) 1 1 0 DMA Channel 0 (DACK6#) 1 1 1 DMA Channel 0 (DACK7#) DMA Cycle Type DMA I/O Address TC (A2) PCI Cycle Type Normal 0000_0000h 0 I/O Read/Write Normal TC 0000_0004h 1 I/O Read/Write Verify 0000_00C0h 0 I/O Read Verify TC 0000_00C4h 1 I/O Read. Figure 3. PC87200 Clock Generation N SYSCLK PCICLK PC87200 |
Similar Part No. - PC87200 |
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Similar Description - PC87200 |
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