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PIC18F4431 Datasheet(PDF) 30 Page - Microchip Technology

Part # PIC18F4431
Description  28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4431 Datasheet(HTML) 30 Page - Microchip Technology

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PIC18F2331/2431/4331/4431
DS39616B-page 28
Preliminary
 2003 Microchip Technology Inc.
REGISTER 2-2:
OSCCON REGISTER
2.7.2
OSCILLATOR TRANSITIONS
The PIC18F2331/2431/4331/4431 devices contain
circuitry to prevent clocking “glitches” when switching
between clock sources. A short pause in the system
clock occurs during the clock switch. The length of this
pause is between 8 and 9 clock periods of the new
clock source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
R/W-0
R/W-0
R/W-0
R/W-0
R(1)
R-0
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
bit 7
bit 0
bit 7
IDLEN: Idle Enable bit
1
= Idle mode enabled; CPU core is not clocked in power-managed modes
0
= Run mode enabled; CPU core is clocked in power-managed modes
bit 6-4
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111
= 8 MHz (8 MHz source drives clock directly)
110
= 4 MHz
101
= 2 MHz
100
= 1 MHz
011
= 500 kHz
010
= 250 kHz
001
= 125 kHz
000
= 31 kHz (INTRC source drives clock directly)
bit 3
OSTS: Oscillator Start-up Time-out Status bit
1
= Oscillator start-up time-out timer has expired; primary oscillator is running
0
= Oscillator start-up time-out timer is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1
= INTOSC frequency is stable
0
= INTOSC frequency is not stable
bit 1-0
SCS1:SCS0: System Clock Select bits
1x
= Internal oscillator block (RC modes)
01
= Timer1 oscillator (Secondary modes)
00
= Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of the IESO bit in Configuration Register 1H.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown


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