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PCF8598C-2T Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCF8598C-2T Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 24 page 1997 Feb 13 8 Philips Semiconductors Product specification 256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family 8.3 Device addressing Following a START condition the bus master must output the address of the slave it is accessing. The 4 MSBs of the slave address are the device type identifier (see Fig.5). For the PCF85xxC-2 this is fixed to ‘1010’. The next three significant bits address a particular device or memory page (page = 256 bytes of memory). A system could have up to eight PCF8582C-2 (or four PCF8594C-2 containing two memory pages each or two PCF8598C-2 containing four memory pages each, respectively) devices on the bus. The eight addresses are defined by the state of the A0, A1 and A2 inputs. The last bit of the slave address defines the operation to be performed. When set to logic 1 a read operation is selected. Address bits must be connected to either VDD or VSS. 8.4 Write operations 8.4.1 BYTE/WORD WRITE For a write operation the PCF85xxC-2 requires a second address field. This address field is a word address providing access to the 256 words of memory. Upon receipt of the word address the PCF85xxC-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master can now terminate the transfer by generating a STOP condition or transmit up to six more bytes of data and then terminate by generating a STOP condition. Fig.5 Slave address. handbook, halfpage MBC793 101 0 A2 A1 A0 R/W After this STOP condition the E/W cycle starts and the bus is free for another transmission. Its duration is 10 ms per byte. During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus. 8.4.2 PAGE WRITE The PCF85xxC-2 is capable of an eight-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transmit eight data bytes within one transmission. After receipt of each byte the PCF85xxC-2 will respond with an acknowledge. The typical E/W time in this mode is 9 × 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms and sequential writing of these 8 bytes another typical 28 ms. After the receipt of each data byte the three low order bits of the word address are internally incremented. The high order five bits of the address remain unchanged. The slave acknowledges the reception of each data byte with an ACK. The I2C-bus data transfer is terminated by the master after the 8th byte with a STOP condition. If the master transmits more than eight bytes prior to generating the STOP condition, no acknowledge will be given on the ninth (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles. 8.4.3 REMARK A write to the EEPROM is always performed if the pin WP is LOW (not on PCF8582C-2). If WP is HIGH, then the upper half of the EEPROM is write-protected and no acknowledge will be given by the PCF85xxC-2 when one of the upper 256 EEPROM bytes (PCF8594C-2) or 512 EEPROM bytes (PCF8598C-2) is addressed. However, an acknowledge will be given after the slave address and the word address. |
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