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P87C51MB2 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. P87C51MB2
Description  80C51 8-bit microcontroller family with extended memory
Download  34 Pages
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com

P87C51MB2 Datasheet(HTML) 2 Page - NXP Semiconductors

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2001 Apr 06
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
The P87C51Mx2 represents the first microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2
features 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbytes of OTP and 2
Kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be
configured to different time ranges through SFR bits, as well as two enhanced UARTs or one enhanced UART and an SPI.
Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice
the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of
program memory and 8Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use
80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51
bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits
The P87C51Mx2 provides greater functionality, increased performance and overall lower system cost. By offering an embedded
memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for
software work-arounds. The increased program memory enables design engineers to develop more complex programs in a high-
level language like C, for example, without struggling to contain the program within the traditional 64 Kbytes of program memory.
These enhancements also greatly improve C Language efficiency for code size below 64 Kbytes.
The 51MX core is described in more details in the 51MX Architecture Reference.
• Extended features of the 51MX Core:
- 23-bit program memory space and 23-bit data memory space - linear program and data address range expanded to sup-
port up to 8 Mbytes each
- Program counter expanded to 23 bits
- Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation
- New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using
pointers to access variables in different spaces.
• 100% binary compatibility with the classic 80C51 so that existing code is completely reusable
• Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
• 96 Kbytes or 64 Kbytes of on-chip OTP
• 3 Kbytes or 2 Kbytes of on-chip RAM
• Programmable Counter Array (PCA)
• Two full-duplex enhanced UARTs
• Industry-standard Serial Peripheral Interface (SPI)
• Increases program/data address range to 8 Mbytes each
• Enhances performance and efficiency for C programs
• Fully 80C51-compatible microcontroller
• Provides seamless and compelling upgrade path from classic 80C51
• Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs
• Supported by 80C51 development and programming tools (Keil, Nohau, BP Micro, etc.)
• The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market

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