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PC16552D Datasheet(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. PC16552D
Description  Dual Universal Asynchronous Receiver/Transmitter with FIFOs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC16552D Datasheet(HTML) 1 Page - National Semiconductor (TI)

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June 1995
Dual Universal Asynchronous
ReceiverTransmitter with FIFOs
General Description
The PC16552D is a dual version of the PC16550D Universal
Asynchronous ReceiverTransmitter (UART) The two serial
channels are completely independent except for a common
CPU interface and crystal input On power-up both channels
are functionally identical to the 16450
Each channel can
operate with on-chip transmitter and receiver FIFOs (FIFO
mode) to relieve the CPU of excessive software overhead
In FIFO mode each channel is capable of buffering 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) of data
in both the transmitter and receiver All the FIFO control
logic is on-chip to minimize system overhead and maximize
system efficiency
Signalling for DMA transfers is done through two pins per
channel (TXRDY and RXRDY) The RXRDY function is mul-
tiplexed on one pin with the OUT 2 and BAUDOUT func-
tions The CPU can select these functions through a new
register (Alternate Function Register)
Each channel performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM
and parallel-to-serial conversion on data characters re-
ceived from the CPU The CPU can read the complete
status of each channel at any time Status information re-
ported includes the type and condition of the transfer opera-
tions being performed by the DUART as well as any error
conditions (parity overrun framing or break interrupt)
The DUART includes one programmable baud rate genera-
tor for each channel Each is capable of dividing the clock
input by divisors of 1 to (216 b 1) and producing a 16 c
clock for driving the internal transmitter logic Provisions are
also included to use this 16 c clock to drive the receiver
logic The DUART has complete MODEM-control capability
and a processor-interrupt system Interrupts can be pro-
grammed to the user’s requirements minimizing the com-
puting required to handle the communications link
The DUART is fabricated using National Semiconductor’s
advanced M2CMOSTM
Dual independent UARTs
Capable of running all existing 16450 and PC16550D
After reset all registers are identical to the 16450 reg-
ister set
Read and write cycle times of 84 ns
In the FIFO mode transmitter and receiver are each
buffered with 16-byte FIFOs to reduce the number of
interrupts presented to the CPU
Holding and shift registers in the 16450 Mode eliminate
the need for precise synchronization between the CPU
and serial data
Adds or deletes standard asynchronous communication
bits (start stop and parity) to or from the serial data
Independently controlled transmit receive line status
and data set interrupts
Programmable baud generators divide any input clock
by1to(216 b 1) and generate the 16 c clock
MODEM control functions (CTS RTS DSR DTR RI
and DCD)
Fully programmable serial-interface characteristics
5- 6- 7- or 8-bit characters
Even odd or no-parity bit generation and detection
1- 1
- or 2-stop bit generation
Baud generation (DC to 15M baud) with 16 c clock
False start bit detection
Complete status reporting capabilities
TTL drive for the data and control buses
Line break generation and detection
Internal diagnostic capabilities
Loopback controls for communications link fault
Break parity overrun framing error simulation
Full prioritized interrupt system controls
Can also be reset to 16450 Mode under software control
Note This part is patented
is a registered trademark of National Semiconductor Corporation
M2CMOSTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75Printed in U S A

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