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PC16552D Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. PC16552D
Description  Dual Universal Asynchronous Receiver/Transmitter with FIFOs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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PC16552D Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
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30 AC Electrical Characteristics TA e 0 Cto a70 C VDD ea5V g10%
Symbol
Parameter
Conditions
Min
Max
Units
tAR
RD Delay from Address
15
ns
tAW
WR Delay from Address
15
ns
tDH
Data Hold Time
5
ns
tDS
Data Setup Time
15
ns
tHZ
RD to Floating Data Delay
(Note 2)
10
20
ns
tMR
Master Reset Pulse Width
500
ns
tRA
Address Hold Time from RD
0ns
tRC
Read Cycle Update
29
ns
tRD
RD Strobe Width
40
ns
tRVD
Delay from RD to Data
25
ns
tWA
Address Hold Time from WR
0ns
tWC
Write Cycle Update
29
ns
tWR
WR Strobe Width
40
ns
tXH
Duration of Clock High Pulse
External Clock (24 MHz Max)
17
ns
tXL
Duration of Clock Low Pulse
External Clock (24 MHz Max)
17
ns
RC
Read Cycle e tAR a tRD a tRC
84
ns
WC
Write Cycle e tAW a tWR a tWC
84
ns
BAUD GENERATOR
N
Baud Divisor
1
216 b 1
tBHD
Baud Output Positive Edge Delay
fX e 24 MHz d245
ns
tBLD
Baud Output Negative Edge Delay
fX e 24 MHz d245
ns
RECEIVER
tRAI
Delay from Active Edge of RD to
78
ns
Reset Interrupt
tRINT
Delay from Inactive Edge of RD
(RD LSR)
40
ns
to Reset Interrupt
tRXI
Delay from READ to RXRDY Inactive
55
ns
tSCD
Delay from RCLK to Sample Time
33
ns
tSINT
Delay from Stop to Set Interrupt
(Note 1)
2
BAUDOUT
Cycles
Note 1
In the FIFO mode (FCR0 e 1) the trigger level interrupts the receiver data available indication the active RXRDY indication and the overrun error
indication will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes
these indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs
Note 2
Charge and discharge time is determined by VOL VOH and the external loading
Note 3
All AC timings can be met with current loads that don’t exceed 32 mA or b80 mA at 100 pF capacitive loading
Note 4
For capacitive loads that exceed 100 pF the following typical derating factors should be used
100 pF k CL s 150 pF t e (01 nspF)(CL b 100 pF)
150 pF k CL s 200 pF t e (008 nspF)(CL b 100 pF)
ISINK
t e (05 nsmA)(ISINK mA)
ISOURCE
t e (05 nsmA)(ISOURCE mA)
Limits ISOURCE is negative ISINK s 48 mA ISOURCE s b120 mA CL s 250 pF
AC Testing Load Circuit
TLC9426 – 22
4


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